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[[Image:chipsandcircuits2.jpg|thumb|right|]] | [[Image:chipsandcircuits2.jpg|thumb|right|]] | ||
| + | ==Warning== | ||
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| + | Although this assignment has been simplified, it might still be quite hard. | ||
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==Introduction== | ==Introduction== | ||
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==Assignment== | ==Assignment== | ||
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{| align="center" | style=" align="center"; text-align: center; margin-left: 1em; margin-bottom: 1em; font-size: 100%;" | {| align="center" | style=" align="center"; text-align: center; margin-left: 1em; margin-bottom: 1em; font-size: 100%;" | ||
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| − | |valign=" | + | |valign="bottom" |[[Image:print1.gif|frame| Print #1]] |
| − | |valign=" | + | |valign="bottom" |[[Image:print2.gif|frame| Print #2]] |
|} | |} | ||
</Center> | </Center> | ||
| + | Print #1 and Print #2 are arrangements of gates on a base, and all it takes is to wire the appropriate gates together. There are three net lists for each print. Each net list needs to be implemented. The gates are numbered from left to right and from top to bottom. Nets can only follow the grid, one step costs 1 unit length. Nets can also go up and down to lower and higher layers, also at the cost of 1 per level. The assignment is to implement all nets in all netlists at minimum cost. | ||
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Revision as of 19:41, 19 October 2014
Warning
Although this assignment has been simplified, it might still be quite hard.
Introduction
Chips (or more precisely: integrated circuits) are found in your PC, MacBook, Android Phone and microwave oven where they perform a diversity of functions, ranging from timekeeping and motor control to arithmetic and logic. Basically a small plate of silicon, chips are usually designed logically and subsequentially transformed to a list of connectable gates. This list, commonly known as a net list is finally transformed into a 2-dimensional design on a silicon base.
This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements on the base lead to short connections, leading to faster circuits, whereas poor arrangements lead to slower circuits. It leads to no doubt that a good arrangement of logical gates and good wiring between them is of vital essence to the performance of the IC as a whole.
To make things easier, we will consider the wiring problem only. The gates have already been arranged, and all it takes is finding very short wiring patterns.
Example
 Netlist #1 |
 Een suboptimale wiring voor netlist #1. |
 De optimale wiring voor netlist #1. |
This is an integrated circuit built up from five gates that need to be connected. The connections ("nets") follow the grid in a Manhattan style. Luckily enough, the wires don't cross. Sometimes they have to and when they do, the base consists of multiple grid layers. Besides going North, South, East and West, nets can also go up and down, and the distance between levels is identical to the distance between grid points.
Assignment
 Print #1 |
 Print #2 |
Print #1 and Print #2 are arrangements of gates on a base, and all it takes is to wire the appropriate gates together. There are three net lists for each print. Each net list needs to be implemented. The gates are numbered from left to right and from top to bottom. Nets can only follow the grid, one step costs 1 unit length. Nets can also go up and down to lower and higher layers, also at the cost of 1 per level. The assignment is to implement all nets in all netlists at minimum cost.
Advanced
For each of the three arrangements, try to determine the relation between the number of wires and the required number of layers.
Links
No links.
Terug
Back to the Heuristics main page.