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==Example #1== | ==Example #1== | ||
− | Given | + | Given netlist#1, connecting five logical gates on a grid. Gates cannot be on directly adjacent grid points because of the produced heat. They should be connected in exact correspondence to the netlist, though connections can be considered to be undirected for the scope of this case. Gates to not have an in- or output side; connections can enter or exit at any point from a gate. Connections must follow grid lines for reasons of manufacture, but connections between different gates cannot cross. |
{| border="1" | {| border="1" | ||
!'''Netlist #1:''' | !'''Netlist #1:''' | ||
|- | |- | ||
− | ! A||B, | + | ! A||B,C; |
|- | |- | ||
! C||E; | ! C||E; | ||
Line 33: | Line 33: | ||
|} | |} | ||
</Center> | </Center> | ||
+ | |||
+ | |||
+ | As can be seen | ||
==Assignment== | ==Assignment== |
Revision as of 09:56, 5 April 2014
Introduction
Chips (or more precisely: integrated circuits) are found in your PC, MacBook, Android Phone and microwave oven where they perform a diversity of frunctions, ranging from timekeeping and motor control to arithmetical calculations. Basically a small plate of silicon supporting a considerable number of connected logical gates, chips are usually designed by a logical design, subsequentially transformed to a list of connectable logical gates (commonly known as a net list) and in the final step transformed to 2-dimensional design on a silicon base.
This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements on the base lead to short connections, leading to faster circuits, whereas poor arrangements lead to slower circuits. It leads to no doubt that a good arrangement of logical gates is of vital essence to the value of the IC as a whole.
Example #1
Given netlist#1, connecting five logical gates on a grid. Gates cannot be on directly adjacent grid points because of the produced heat. They should be connected in exact correspondence to the netlist, though connections can be considered to be undirected for the scope of this case. Gates to not have an in- or output side; connections can enter or exit at any point from a gate. Connections must follow grid lines for reasons of manufacture, but connections between different gates cannot cross.
Netlist #1: | |
---|---|
A | B,C; |
C | E; |
D | B; |
E | C,D |
thumb Game #2 |
---|
As can be seen
Assignment
1) Design a chip from netlist#1.
2) Design a chip from netlist#2.
3) Design a chip from netlist#3.
Advanced
The suspicion is, that the minimal number of layers required for a chip to be designed from a netlist depends on the connectivity of the netlist. Generate 10 random netlists with the exact same number of gates and connections as in netlist#3 and run them through your algorithm. Carefully document the number of layers needed and the optimality of the found solution. Next, double the number of connections for each netlist and run them through your algorithm again. Document carefully again, and compare the results with the previous experiment.
Links
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