Chips & Circuits - Revision history

MeesterDaan: /* Questions & Answers */

2018-10-15T10:15:29Z

‎Questions & Answers

MeesterDaan at 10:08, 15 October 2018

2018-10-15T10:08:52Z

MeesterDaan: /* Advanced */

2018-10-15T10:08:22Z

‎Advanced

MeesterDaan at 09:54, 15 October 2018

2018-10-15T09:54:25Z

MeesterDaan at 09:47, 15 October 2018

2018-10-15T09:47:01Z

MeesterDaan at 09:28, 15 October 2018

2018-10-15T09:28:23Z

MeesterDaan at 22:21, 13 February 2018

2018-02-13T22:21:58Z

MeesterDaan at 22:20, 13 February 2018

2018-02-13T22:20:14Z

MeesterDaan: /* Questions & Answers (November 2nd, 2014) */

2015-04-18T22:55:34Z

‎Questions & Answers (November 2nd, 2014)

MeesterDaan: /* Assignment */

2015-04-18T22:49:12Z

‎Assignment

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 '''3) A new layer, should it be somewhere specific, or can we place it where we want?'''
-A new (second, third, fourth) layer provides a means for your nets to go down one level. So, if you add a level to your chip, it is everywhere. But, if a layer (for instance a seventh or eight layer) is unused, it should not be placed of course, to keep manufacturing costs down.
+A new (second, third, fourth) layer provides a means for your nets to go down one extra level. A new layer is of equal dimensions as the original base. But, if a layer (for instance a seventh or eight layer) is unused, it should not be placed of course, to keep manufacturing costs down.
 '''4) Can unconnected gates be removed?'''
-I hope that this issue has been addressed. I expect not to have any unconnected nets left.
+We have updated the net lists and gate configurations. No unconnected gates exist anymore.
-'''5) Can unconnected gates be regarded "null" and may nets run through them?'''
+'''5) Can nets run through gates?'''
-I hope that this issue too, has been addressed. Otherwise: no!
+No! Every net touches exactly two gates, one at both ends.
 '''6) Can loose segments of several logical gates be distributed elsewhere on the base?'''
-No. Even if there are still any of these, I don't want it in this version of Chips and Circuits. Easier versions allowed gates to be moved, and with those degrees of freedom, the case was way too hard.
+We don't expect this situation to be present, but the answer in any case is no; gate locations are fixed.
 ==Links==

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 ==Assignment==
 <Center>
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 * Randomly generate some new net lists. They should be of equal length to the original net lists. Which are solvable, which aren't? Which have good solutions, which haven't?
 ==Questions & Answers ==

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 ==Advanced==
-For each of the three arrangements, try to determine the relation between the number of wires and the required number of layers.
+* Randomly generate some new net lists. They should be of equal length to the original net lists. Which are solvable, which aren't? Which have good solutions, which haven't?
 ==Questions & Answers ==

← Older revision		Revision as of 09:54, 15 October 2018
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−	This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements with short nets lead to faster circuits, whereas poor arrangements with long nets lead to slower circuits. ~~There~~ is no doubt that a good arrangement of logical gates and short nets between them is of vital importance ~~to the performance of the IC as a whole~~.	+	This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements with short nets lead to faster circuits, whereas poor arrangements with long nets lead to slower circuits. Besides, shorter nets are cheaper than long nets, so there is no doubt that a good arrangement of logical gates and short nets between them is of vital importance, both economically and performancewise.


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−	This is an integrated circuit built up from five gates that need to be connected. The connections ("nets") follow the grid in a Manhattan style. Luckily enough, the wires don't cross. Sometimes they have to and when they do, the base consists of multiple grid layers. Besides going North, South, East and West, nets can also go up and ~~down~~, and the distance between levels is identical to the distance between grid points.	+	This is an integrated circuit built up from five gates that need to be connected. The connections ("nets") follow the grid in a Manhattan style. Luckily enough, the wires don't cross. Sometimes they have to and when they do, the base consists of multiple grid layers. Besides going North, South, East and West, nets can also go Up and Down, and the distance between levels is identical to the distance between grid points.

← Older revision		Revision as of 09:47, 15 October 2018
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−	This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements ~~on the base~~ lead ~~to short connections, leading~~ to faster circuits, whereas poor arrangements lead to slower circuits. ~~It leads to~~ no doubt that a good arrangement of logical gates and ~~good wiring~~ between them is of vital ~~essence~~ to the performance of the IC as a whole.	+	This last step however, the physical real-world process of connecting the gates, is highly volatile. Good arrangements with short nets lead to faster circuits, whereas poor arrangements with long nets lead to slower circuits. There is no doubt that a good arrangement of logical gates and short nets between them is of vital importance to the performance of the IC as a whole.

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 [[Image:chipsandcircuits2.jpg|thumb|right|]]
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 </Center>
-Print #1 and Print #2 are arrangements of gates on a base, and all it takes is to wire the appropriate gates together. There are three net lists (in [http://heuristieken.nl/resources/CC_netlists2.txt txt-format]) for each print. Each net list needs to be implemented. Nets can only follow the grid, only one wire per segment, and one step costs 1 unit length. Nets that are aligned among the same grid line are said to be in <I>conflict</I>. If there is one conflict in one arrangement, the circuit cannot be used. Nets can also go up and down to lower and higher layers, also at the cost of 1 per level. The assignment is to implement all nets in all netlists at minimum cost.
+Print #1 and Print #2 are arrangements of gates on a base, and all it takes is to wire the appropriate gates together. There are three net lists (in [http://heuristieken.nl/resources/CC_netlists2.txt txt-format]) for each print. Each net list needs to be implemented. Nets can only follow the grid, only one wire per segment, and one step costs 1 unit length. Nets that are aligned among the same grid line are said to be in <I>collision</I>. If there is one collision in one arrangement, the circuit cannot be used. Nets can also go up and down to lower and higher layers, also at the cost of 1 per level. The assignment is to implement all nets in all netlists at minimum cost.
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-) Expand your program by making a data structure for a net list. Make sure it holds a few nets, and that the program calculates the total wire length.
+) Expand your program by making a data structure for a net list. Make sure it holds a few nets, and that the program has a cost function to calculate the total wire length.
-) Add 7 more layers. Try to get all the nets in. You can either build up wire-by-wire and step-by,step or with all wires in place, suboptimal and conflictuous, and try to improve. Whatever you do: record data to analyze for your report.
+) Try to get all the nets in with minimal costs. Record all your results, so you can present them later.

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 Although this assignment has been simplified, it might still be quite hard.
 ==Introduction==
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 ) Add 7 more layers. Try to get all the nets in. You can either build up wire-by-wire and step-by,step or with all wires in place, suboptimal and conflictuous, and try to improve. Whatever you do: record data to analyze for your report.
 ==Advanced==
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 No. Even if there are still any of these, I don't want it in this version of Chips and Circuits. Easier versions allowed gates to be moved, and with those degrees of freedom, the case was way too hard.
 ==Links==

← Older revision		Revision as of 22:20, 13 February 2018
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−	==Questions & Answers ~~(November 2nd, 2014)~~ ==	+	==Questions & Answers ==

	'''1) "only one wire per segment", does this means multiple nets can use a grid intersection?'''		'''1) "only one wire per segment", does this means multiple nets can use a grid intersection?'''